This page is dedicated to my fist microprocessor, the INS8060, also called the SC/MP processor. At the time I was 13 years old and did not have much money, I could afford to buy an electronics magazine called Elektuur every month, and they published a simple computer board based on the SC/MP processor. I was very interested in computer technology at that time and I read all I could about the SC/MP processor. As I did not have the money to buy a board I would draw the internal of the processor on a big piece of paper, with the RAM / ROM / keyboard and display as registers and I would have a lot of small zero and one papers to simulate the flow of the bits and bytes in the (paper) circuit. Looking back this was ridiculous, but this is the way I learned computer design and binary logic. By the time I learned the Z80 system I had good knowledge of processors and binary logic. I also saw a board called the MK14 that was based on the SC/MP as well, I considered buying one at the time, but I decides to go for a real computer. Still the SC/MP is my first processor and nowadays you cannot get the processor anymore (at least not at a reasonable price), but there are emulators in software and hardware that are still available. I have to say that I recemtly bought a SC/MP processor in China for 20 Euros. On this page I will share all documentations, links, schematics and code that I have or have found. Regards, Hein Pragt.
I also have a Facebook Group on Retro Computing and Electronics, feel free to join!
About the INS8060 or SC/MP Processor
National Semiconductor introduced the INS8060 or SC/MP In April 1976 and it was intended for small and cheap industrial controllers. The acronym SC/MP stands for Small Cost-effective Micro Processor and it needed few external components and was simple to program. In 1977 Elektor Magazine devoted a few issues to the SC/MP and the Elektor design came in two versions, a simple basic one and a version with a hexadecimal keyboard, 7-segment displays and a monitor program in ROM, cassette interface and the option to connect a VDU. The INS8060 or SC/MP has a rather simple architecture and can address a total of 65536 bytes memory. Because only 12 of these address lines are connected to pins the addressing space is 4 kb bute the high four bits of the address were multiplexed on the data bus during the NADS-signal. The 64k memory is divided in 16 x 4096-bytes pages. Only a limited number of memory reference instructions can cross a page boundary.
The first INS8060 or SC/MP chip was developed in P-MOS technology and needed a positive power supply of 5 Volts and a negative of 7 Volts. Later National Semiconductor introduced the SC/MP-II that was made in N-MOS technology and only needed a single 5 Volt power. Three of the signals on the SC/MP-II were logically reversed (i.e. BREQ became NBREQ) so the SC/MP-II is not 100% pin-compatible with the first SC/MP-I. The INS8060 or SC/MP was not a powerful microprocessor but at the time it was cheap and simple to use. The SC/MP only an instruction set of 46 basic instructions and was rather easy to program at binary level. Beside the Elektor design there was also a one board computer implementation called the MK14, developed by Science of Cambridge Ltd, which was a company of Sir Clive Sinclair. These are still sold on Ebay sometimes but there are also great emulators in software and hardware. (PIC microcontroller).
INS8060 or SC/MP Pinout
The table below describes the various SC/MP signals and pinouts.
(A preceding “N” in the signal mnemonic signifies a negative active signal.)
| NRST | Reset Input | Set high for normal operation. When set low, aborts in-process operations. When returned high, internal control circuit zeroes all programmer-accessible registers; then, first instruction is fetched from memory location &H0001 |
| CONT | Continue Input | When set high, enables normal execution of program stored in external memory. When set low, SC/MP operation is suspended (after completion of current instruction) without loss of internal status |
| NBREQ * | Bus Request In/Output | Associated with SC/MP Internal allocation logic for system bus. Can be used as bus request output or bus busy input. Requires external load resistor to Vcc |
| NENIN * | Enable Input | Associated with SC/MP Internal location logic for system bus. When set low, SC/MP Is granted access to system busses. When set high, places system busses in high-impedance (TRI-STATE) mode. |
| NENOUT * | Enable Output | Associated with SC/MP Internal allocation logic for system bus. Set low when NENIN is low and SC/MP Is not using system busses (NBREQ-high. Set high at all other times.) |
| NADS | Address Strobe Output | Active-low strobe. While low, indicates that valid address and status output are present on system busses. |
| NRDS | Read Strobe Output | Active-low strobe. On trailing edge, data are input to SC/MP from 8-bit bi-directional data bus. High-impedance (TRI-STATE) output when input/output cycle is not in progress. |
| NWDS | Write Strobe Output | Active-low strobe. While low, indicates that valid output data are present on 8-bit bi-directional data bus. High-impedance (TRI-STATE) output when input/output cycle is not in progress. |
| NHOLD | Input/Output Cycle Extend Input | When set low prior to trailing edge of NRDS or NWDS strobe, stretches strobe to extend input/output cycle; that is, strobe is held low until NHOLD signal is returned high. (for slow memory) |
| SENSE A | Sense/Interrupt Request Input | Serves as interrupt request input when SC/MP Internal IE (Interrupt Enable) flag is set. When IE flag is reset, serves as user-designated sense condition input. Sense condition testing is effected by copying status register to accumulator. |
| SENSE B | Sense Input | User-designated sense-condition input. Sense-condition testing is effected by copying status register to accumulator. |
| SIN | Serial Input to E register | Under software control, data on this line are right-shifted into E register by execution of SIO instruction. |
| SOUT | Serial Output from E register | Under software control, data are right-shifted onto this line from E register by execution of SIO instruction. Each data bit remains latched until execution of next SIO instruction. |
| FLAGS 0,1,2 | Flags Outputs | User-designated general-purpose flag outputs of status register. Under program control, flags can be set and reset by copying accumulator to statusregister. |
| AD00-AD11 | Address bits 00 through 11 | Twelve (TRI-STATE) address output lines. SC/MP outputs 12 least significant address bits on this bus when NADS strobe is low. Address bits are then held valid until trailing edge of read (NRDS) or write (NWDS) strobes. After trailing edge of NRDS or NWDS strobe, bus is set to high (TRI-STATE) mode until next NADS strobe. |
| Databus | Output at NADS Time | During NADS time the four most significant bits of the addressbus are active at the outputs. Also some other special signals are available at the remaining database pinouts. |
| DB0 | Address Bit 12 | Fourth most significant bit of 16-bit address |
| DB1 | Address Bit 13 | Third most significant bit of 16-bit address |
| DB2 | Address Bit 14 | Second most significant bit of 16-bit address |
| DB3 | Address Bit 15 | Most significant bit of 16-bit address |
| DB4 | R-Flag | When high, data input cycle is starting; when low, data output cycle is starting |
| DB5 | I-Flag | When high, first byte of instruction is being fetched |
| DB6 | D-Flag | When high, indicates delay cycle is started; that is, second byte of DLY instructions being fetched |
| DB7 | H-Flag | When high, indicates that HALT instruction has been executed. (In some system configurations, the H-Flag output is latched and, in conjunction with the CONTinue input, provides a programmed halt). |
| Databus | Standard Output | |
| DB0-DB7 | Databus input/output | During the assertion of NWDS or NRDS data is written to or read from external devices. Except for NADS-time, at all other times the databus is floated in (TRI-STATE) modus. |
| Vcc | Plus 5 volts | Power lead |
| GND * | Ground (0 Volts) | Power ground lead SC/MP-II (P-MOS) |
| Vgg | Minus 7 Volts | Power negative lead SC/MP-I (N-MOS) |
| XIN/ XOUT | Clock Crystal inputs | A quarts crystal between these leads will determine the clock-frequency of the SC/MP CPU. The SC/MP-II has an internal divide stage so its clock-frequency divided by two. |
INS8060 or SC/MP Instruction format
The SC/MP executes either 1 or 2 byte instructions, the first byte is called the OPCODE the optional second byte is the OPERAND. When the most significant bit of the OPCODE is set to 1 it will be a 2 byte instruction, the programcounter (P0) is automatically incremented to fetch the OPERAND byte. Most 2 byte instructions are memory reference instruction that will access memory external to the CPU. With the exception of the ILD and the DLD instruction the SC/MP will initiate a single byte read or write memory access, the ILD and the DLD instruction will do a read-modify-write instruction.
The internal register set of the INS8060 or SC/MP is VERY simple, it has only a few internal registers.
Accu
This is a standard accumulator register that contains the result of the most operations and usually holds one of the source operands.
Extension
The extensionregister has a multi purpose usage, it can be used to hold secondary operands to the extension instructions, it can be also be used to temporarily save the accu and it can be used as an 8-bit index register to facilitate relative indirect addressing. Whenever the 2nd byte operand of a memory reference instruction (called the displacement) holds a value of &H80 the content of the extension register is taken as the displacement instead of the 2nd byte operand. Also the extension register is used for the build in serial I/O capability of the SC/MP. The MSB of the extension register is connected to the SIN input and the LSB is connected to the SOUT output line.
Status
The status register contains a number of standard flags like the carry flag and the overflow flag and the interupt enable flag. However, the carry and overflow flags are not directly tested by branch-instructions. They must be copied to the accu first (CAS-instruction) and their state must be ascertained with bitwise logical instructions. Branch testing is only done on the state of the accu-register. Flag F0, F1 & F2 are connected to the flag pins for output. Sense SA & SB that are connected to the sense input pins.
The Pointer Registers P0-P3
The Pointer registers P1-P3 are used as datapointer, stackpointer and subroutine / interupt service pointers. Pointer register P0 is used as the Programcounter, the main difference with a normal programcounter is the fact that the SC/MP PC is incremented prior to fetching a new instruction, so the program always continues the next instruction at PC+1. Another feature of all pointer registers is that whenever a pointer-register is incremented by a auto indexed addressing mode instruction or an effective address is calculated that crosses a page boundary, the effective address folds back to the beginning of the page. Only when loading an absolute address into the pointer register the page boundary can be crossed! National Semiconductor recommends the following pointer register roles as a rule of thumb: P0 = Program Counter, P1 = Data of I/O Pointer, P2 = Stackpointer, P3 = Subroutine/interrupt Pointer. The XPPC instruction can exchange the content of the PC with any of the other pointer-registers so any Px can service a subroutine but only P3 can service a service routine for an interupt, because the XPPC3 instruction is generated automatically whenever an interupt is received.
INS8060 or SC/MP addressing Modi
All memory reference instructions make use of addressing modes to calculate the effective address of the memory reference. This could be to access the content of a memory location but also to determine the target adress of a branch or jump instruction. The SC/MP features the following addressingmodes:
PC Relative/Pointer-register Indexed Addressing
The 2nd byte of an instruction is taken as a displacement in 2s complement fashion and added to the current content of the designated pointer register to calculate the effective address. When the PC (P0) is used as the designated pointer register we call this PC relative mode. A 2s complement 8 bit value can contain any value from 127 dec to +127 dec. In the case of a PC relative Jump (branch) one should take into consideration the the programcounter will be incremented by 1, prior to the next opcode fetch.
Indirect Addressing
In SC/MP documentation indirect addressing is regarded as a special case of PC-relative and indexed addressing, in the event that the second byte of an memory reference instruction contains &H80 as a displacement value it is not taken as a negative displacement of 128 dec, but the content of the extension register is used as the 2s complement displacement to calculate the effective address.
Immediate Addressing
The second value of the instruction in a memory reference instruction is immediately used as source data for the instruction, no further address calculation is required.
Auto Indexed Addressing
This addressing mode is a bit like Indexed addressing but this time the pointer register itself is modified by the displacement in a pre decrement and post increment way. In the case of a negative displacement the pointer register is replaced with the effective address and then the memory access is executed. In the case of a positive displacement the memory access is executed with the current value of the designated pointer register, prior to replacing Px with the new modified calculated EA value. In this way we can used P1, P2 or P3 as a LIFO stackpointer.
| Mnemonic | @-modes | Opcode1 | Opcode2 | Type | Flags | Description | |
| C | O | ||||||
| ADD | @DISP(X) | 1111.0maa | pppp.pppp | MR | X | X | Binary ADD mem. w. Carry |
| ADE | e | 0111.0000 | E | X | X | Binary ADD extension w. Carry | |
| ADI | i | 1111.0100 | dddd.dddd | I | X | X | Binary ADD immediate w. Carry |
| AND | @DISP(X) | 1101.0maa | pppp.pppp | MR | Logical AND accu w. mem. | ||
| ANE | e | 0101.0000 | E | Logical AND accu w. extension | |||
| ANI | i | 1101.0100 | dddd.dddd | I | Logical AND accu immediate | ||
| CAD | @DISP(X) | 1111.1maa | pppp.pppp | MR | X | X | ADD memory complement w. Carry |
| CAE | e | 0111.1000 | E | X | X | ADD extension complement w. Carry | |
| CAI | i | 1111.1100 | dddd.dddd | I | X | X | ADD immediate complement w. carry |
| CAS | st | 0000.0111 | ST | ! | ! | Move Accu to Status | |
| CCL | cy | 0000.0010 | M | F | Clear Carry-flag | ||
| CSA | st | 0000.0110 | ST | Move Status to Accu | |||
| DAD | @DISP(X) | 1110.1maa | pppp.pppp | MR | X | Decimal ADD memory w. Carry | |
| DAE | e | 0110.1000 | E | X | Decimal ADD extension w. Carry | ||
| DAI | i | 1110.1100 | dddd.dddd | I | X | Decimal ADD immediate w. Carry | |
| DINT | 0000.0100 | M | Disable Interrupt | ||||
| DLD | DISP(X) | 1011.10aa | pppp.pppp | MR | Decrement & Load memory | ||
| DLY | i | 1000.1111 | dddd.dddd | M | Delay | ||
| HALT | 0000.0000 | M | Halt instruction | ||||
| IEN | 0000.0101 | M | Enable Interrupt | ||||
| ILD | DISP(X) | 1010.10aa | pppp.pppp | MR | Increment & Load memory | ||
| JMP | DISP(X) | 1001.00aa | pppp.pppp | J | Jump Absolute | ||
| JNZ | DISP(X) | 1001.11aa | pppp.pppp | J | Jump Non Zero | ||
| JP | DISP(X) | 1001.01aa | pppp.pppp | J | Jump Positive | ||
| JZ | DISP(X) | 1001.10aa | pppp.pppp | J | Jump Zero | ||
| LD | @DISP(X) | 1100.0maa | pppp.pppp | MR | Load accu from memory | ||
| LDE | e | 0100.0000 | E | Load accu from extension | |||
| LDI | i | 1100.0000 | dddd.dddd | I | Load accu immediate | ||
| NOP | 0000.1000 | M | No operation | ||||
| OR | @DISP(X) | 1101.1maa | pppp.pppp | MR | Logical OR accu w. memory | ||
| ORE | e | 0101.1000 | E | Logical OR accu w. extension | |||
| ORI | i | 1101.1100 | dddd.dddd | I | Logical OR accu immediate | ||
| RR | 0001.1110 | SR | Rotate right accu | ||||
| RRL | 0001.1111 | SR | X | Logical Rotate right w. Carry | |||
| SCL | 0000.0011 | M | T | Set Carry Flag | |||
| SIO | 0001.1001 | E | Serial I/O extension | ||||
| SR | 0001.1100 | SR | Shift right | ||||
| SRL | 0001.1101 | SR | X | Logical Shift right | |||
| ST | @DISP(X) | 1100.1maa | pppp.pppp | MR | Store accu to memory | ||
| XAE | 0000.0001 | E | Exchange accu w. extension | ||||
| XOR | @DISP(X) | 1110.0maa | pppp.pppp | MR | Logical XOR accu w. memory | ||
| XRE | e | 0110.0000 | E | Logical XOR accu w. extension | |||
| XRI | i | 1110.0100 | dddd.dddd | I | Logical XOR accu immediate | ||
| XPAH x | 0011.01aa | X | Exchange pointer high with accu | ||||
| XPAL x | 0011.00aa | X | Exchange pointer low with accu | ||||
| XPPC x | 0011.11aa | X | Exchange pointer with PC | ||||
The MK14
An well known INS8060 or SC/MP board was the MK14 single board conputer, it was not an Acorn product but a first step in the creation of Acorn Computers. Chris Curry worked
with Clive Sinclair on the development of the MK14 as a Science of Cambridge / Sinclair product. The MK14 was made by Science of Cambridge (later becoming Sinclair Computers and
finally Sinclair Research), it was based on the National Semiconductors SC/MP (INS8060) processor and was sold as as a kit.
National Semiconductor produced quite a lot of other documentation for the SC/MP processor which will be of interest to MK14 owners:
- SC/MP Technical Description
- SC/MP Programming and Assembler Manual
- SC/MP Microprocessor Applications Handbook
Schematics
There were a number of versions of the MK14, the early version schematic is most likely the first version, the later version schematic refers to a version 5 that includes the updated address decoding required for the VDU.
- MK14 Schematic (early version)
- MK14 Schematic (later version)
- MK14 Manual (early version)
- MK14 Manual (later version)
- Address Decoder mods
Firmware
There are two versions of the MK14 monitor program, the first was on the first release of the MK14 and is just National Semiconductors SCMPKB. Then there was an upgrade that included the tape interface routines.
- SCIOS Version 1 Listing (from manual)
- SCIOS Version 1 Binary
- SCIOS Version 1 Binary Low Nibble (White Dot)
- SCIOS Version 1 Binary High Nibble (Blank)
- SCIOS Version 1 Modified Binary
- SCIOS Version 1 Modified Binary Low Nibble (White Dot)
- SCIOS Version 1 Modified Binary High Nibble (Blank)
- SCIOS Version 2 Listing (from manual)
- SCIOS Version 2 Binary
- SCIOS Version 2 Binary Low Nibble (Green Dot)
- SCIOS Version 2 Binary High Nibble (Blue Dot)
The MK14 PIC implementation
I found a very nice MK14 clone on this page an I intend to build this one. The PIC14 program will run in a PIC16F876, Ports A, B and C providing an interface to the display and keyboard. This is a very neat design and a nice piece of programming, it is a hardware clone of the MK14 using a PIC microcontroller.
You can find this project on: Karen’s Microprocessor Projects
INS8060 or SC/MP related documents
- SCMP_Applications_Handbook.pdf SC/MP Microprocessor Applications Handbook (Pdf).
INS8060 or SC/MP links, tips and webpages
- Wikipedia INS8060 or SC/MP page A very complete and intersting page about the INS8060 or SC/MP processor.
- cpu-world SC/MP About the National Semiconductor SC/MP CPU family.
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